Hello! Jim Brain wrote: > I *think* the problem is that the 6502 has an internally generated set > of clocks, while the 6509 expects an external clock. If I look at the > 6500 datasheet, I see that the PHI1/PHI2 on the 6502 trails the incoming > PHI0 clock by some amount, but the amount is not defined in the datasheet. > > Thus, I think, by feeding the incoming PHI2 clock into the 6502, the > 6502 delays it internally and thus is running "out of sync" with the > rest of the bus, which is no doubt synchronized with the external PHI2 > clock on the PCB. This can be indeed a problem. What is the delay in the 6502? I think the only solution would be to create a new clock generation circuit. Regards, Michau. Message was sent through the cbm-hackers mailing listReceived on 2018-02-25 23:01:28
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