> On 2018-03-15, at 01:31, Mia Magnusson <mia@plea.se> wrote: > >> Actually I want to "build" a CPLD based peripheral chip. Let's say a >> port like 6526 but with single port and preferably without feeding it >> with PHI2. > > Aha! I guess that you need PHI2 or use external logic for the > combinations of PHI2 and R/_W as Jim described. If I connect PHI2, this becomes clearer but there are chips working perfectly well without PHI2. Although in such cases the R_W needs to be combined with PHI2, which leads us down... >>> (SRAMs is afaik never affected by spurious short reads, so with >>> those you might get away with timing that don't work well with >>> various I/O stuff). >> >> Sorry for being ignorant here, but what exactly are "spurious short >> reads"? Something like reading chip's own output from the bus? > > I don't know if there is any established term. I'm refering to a > situation where select/enable signals are active when R/_W changes > state. ... here. Because this is *exactly* one of the main reasons I asked the question in the first place! What happens in such situation. When I have a SRAM chip with R_W activation waiting until PHI2 rises, then this should cause the situation you describe. Namely, _CS is already low for some time when R_W goes low. Or am I completely wrong here (can't check it empirically as I am out of my place). > That should ideally not happen but could anyway happen with > imperfect circuits. So how could this be avoided / dealt with? -- SD! - http://e4aws.silverdr.com/Received on 2018-03-15 02:01:03
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