On 3/14/2018 7:33 PM, silverdr@wfmh.org.pl wrote: > So those are separate lines, right? Yep. > The reason I worry is because I don't fully understand how a chip with no PHI2 input doesn't "get confused" whether _CS going low means a read or write cycle. What happens when _CS goes low with R_W remaining high and THEN going low, as it seems to be the case with SRAM, when _CS comes first and then comes R_W due to external combination waiting for PHI2? Isn't this what Mia called "spurious short reads"? In that case, if the CS line goes low with R/W high a read) and *THEN* goes low, you need to treat it as two operations. a read and then a write. If the read cycle (cs low and read high) meets the timing criteria, the read will happen, followed by the write. > > That would imply feeding the chip with PHI2. But memory is not fed with it and still works correctly. Yes, in the Intel space, the WR/RD lines are the defining item. They should be strobed last and finish first. Most of the time, if a chip uses PHI2, internally it is just doing: CSinternal = CSexternal * PHI2 putting the clock in the IC was the Motorola/MOS way of synchronizing the inputs to some known reference. It is not absolutely needed. Jim > -- Jim Brain brain@jbrain.com www.jbrain.comReceived on 2018-03-15 02:01:22
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