Re: Building a 6502 peripheral - timing

On 03/16/2018 07:50 AM, And Fachat wrote:
> The 6502 timing is rather forgiving.
> 
> On reads, enable your databus outputs while phi2 is high, the CPU will 
> take it at the falling edge.
> 
> On writes take the addresd line while phi2 is high and take the data 
> from the bus at the falling edge.
> 
> You can latch the address at the rising edge of phi2 but that prevents 
> working in a bus sharing system like the c64 where the VIC has the bus 
> during phi2 low. That is actually the reason the 6522 does notwork 
> directly in a c64.

VIC does not know about PHI2, it determines who has the bus through PHI0.

  Gerrit