André, thanks a lot for the most thorough response so far. Definitely keeping the ability of the device to work correctly in a shared bus system is important. This brings another questions though: > On 2018-03-16, at 07:50, And Fachat <afachat@gmx.de> wrote: > > On reads, enable your databus outputs while phi2 is high, the CPU will take it at the falling edge.You can latch the address at the rising edge of phi2 but that prevents working in a bus sharing system like the c64 where the VIC has the bus during phi2 low. That is actually the reason the 6522 does notwork directly in a c64. > Also, with " take the address during phi2 high " is critical like in the c64, as the address line may still change at the beginning of the cycle So not on the rising edge but "while". How long / far after the rising edge then? Are there any guidelines for that? Putting aside how to do it correctly in VHDL, because that's another subject. > On writes take the addresd line while phi2 is high and take the data from the bus at the falling edge. Doesn't it imply race condition? I mean if I stop driving the bus on the falling edge, and CPU tries to read it at that very edge? Or is it somehow "guaranteed" that CPU will take the data before PHI2 starts to fall? -- SD!Received on 2018-03-16 18:00:02
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