Re: Building a 6502 peripheral - timing

Am 16. März 2018 17:01:18 schrieb silverdr@wfmh.org.pl:


On 2018-03-16, at 07:50, And Fachat <afachat@gmx.de> wrote:

On reads, enable your databus outputs while phi2 is high, the CPU will take 
it at the falling edge.You can latch the address at the rising edge of phi2 
but that prevents working in a bus sharing system like the c64 where the 
VIC has the bus during phi2 low. That is actually the reason the 6522 does 
notwork directly in a c64.
Also, with " take the address during phi2 high " is critical like in the 
c64, as the address line may still change at the beginning of the cycle

So not on the rising edge  but "while". How long / far after the rising 
edge then? Are there any guidelines for that? Putting aside how to do it 
correctly in VHDL, because that's another subject.

Usually you would let the address lines go through your internal select 
logic and provide the data on the bus once it's there for reads. Make sure 
reads have no side effect like clearing the interrupt as on the 6526 that 
is stupidly broken in that respect. Then it does not matter if address 
lines change during reads, you just provide the data from the different 
location shortly after the address change.

For writes, handle the select logic like on read and pass the select signal 
up until the input latch. Then use the falling edge of phi2 to take in the 
data. To avoid bus contention disable outputs when r/w is low.

This even handles the case where r/w changes from read to write in the 
middle of the cycle. Before the change you put out the data read, after the 
change you disable the outputs and wait for phi2 going low.

The tricky part is when r/w goes from low to high during the cycle while 
phi2 is high. Because usually the input latches are clocked by the

clk =  select AND write AND phi2

If r/w goes to read during the cycle, clk suddenly changes and data is 
latched where it shouldn't. This does not happen on the C64 where the VIC 
only reads, so no problem here but maybe in other setups.

If you need to handle this case you need to delay the rising edge of phi2 
(but of course not the falling edge) until address and r/w are stable.




On writes take the addresd line while phi2 is high and take the data from 
the bus at the falling edge.

Doesn't it imply race condition? I mean if I stop driving the bus on the 
falling edge, and CPU tries to read it at that very edge? Or is it somehow 
"guaranteed" that CPU will take the data before PHI2 starts to fall?

You have to look at the timing diagrams for the signal source and signal 
user. The source usually has a hold time even after the clock or select 
disables it. Also the signal user has a hold timehow long the signal needs 
to be held after the clock transition. These need to match. It gets more 
complicated when you have additional logic in the select, that is why you 
mix phi2 into the latch clock etc as late as possible. And btw those hold 
time specs have min and max values, you need to calculate for the worst 
case. Line capacitance may help to hold data longer but then you plug in a 
module and your timing is broken...

Not sure how much of this can be applied to an fpga, like how much you can 
ensure that phi2 has the shortest path to the latch, or how much hold time 
you can generate after phi2 going down.

That is actually the reason why sometimes replacing some ICs with newer 
versions fails, as they usually are faster and thus timing starts to shift.

In critical cases I nowadays generate correct signals from a higher clock. 
E.g. I use an 8MHz clock, divide by 8 to get phi2, thenuse a shift register 
to create 8 delayed versions of phi2, and combine them e.g. to get DRAM 
control lines.



--
SD!

Hope this helps
André