Re: DMA successes with Verilog

On 14/06/2018 20:42, silverdr@wfmh.org.pl wrote:
> It may be hard to define precisely what is and what is not a CPU in 
> those designs where one cat basically put a whole computer inside a chip

Actually it's not. Lots of SOC have DMA engines alongside a CPU core. 
Both can access the external RAM, the DMA feeds data to other parts of 
the chip while the CPU executes instructions.

The only example that I know of that is hard to define is the ZX80/ZX81. 
You set the program counter to where the screen data is and then detach 
the data bus, so it just executes NOPs. Meanwhile the graphics output 
sees the data being sequentially fetched from RAM. It's not DMA, but 
it's also not PIO.

> The circuit fetches the raw data, processes it and stores the results 
> all by itself, directly accessing memory, without any further help 
> from the CPU

Ok, that is exactly what DMA is. For example MDEC video decompression in 
the original PlayStation used two dma channels, one for the source data 
and one for the destination. Partly because the source and destination 
sizes are different, but it also simplifies the DMA engine. You can DMA 
the source data from CDROM into RAM, then DMA it to MDEC and DMA it back 
to RAM, then DMA to VRAM. The CPU has to coordinate all the transfers 
still. They struggled to make the design fit, or they might have made is 
to that data is read from CD and transferred between components without 
hitting RAM.