Re: DMA successes with Verilog

From: silverdr_at_wfmh.org.pl
Date: Fri, 15 Jun 2018 00:24:27 +0200
Message-Id: <64453F31-C5A0-4DA7-91E7-8E51EA2FC55C@wfmh.org.pl>
> On 2018-06-14, at 23:29, Mia Magnusson <mia@plea.se> wrote:
> 
> Anyways if you really want to know what the CPU is doing you could
> watch the buses. More than two accesses to concecutive addresses means
> that it is fetching from program, i.e. instructions or operands. Then
> it would be easy to see when it accesses some place else, that must be
> data. Backtrace the data bus a bit and then you can be sure where that
> instruction started and where it will end.

AFAIR 6502 has SYNC line that could help but without it are you sure you can never get fooled by a specific data sequence at specific address?

-- 
SD! - http://e4aws.silverdr.com/
Received on 2018-06-15 01:00:45

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