On 21/06/2018 18:13, Jim Brain wrote: > I think this bears figuring out. Given an assumption that your logic > will see all of the same data as the 6502 core, what is the simplest > logic configuration that would generate a new SYNC signal. > What happens if you try to dma at the same time the cpu is going to take an irq? If that is a problem then you would have to pretty much have the entire 6502 core, otherwise you can't know when it's going to take an irq as the cli/sei could be based on the result of calculations. The bus interface would be different as you don't want to perform any reads or writes. You might want to check the addresses match for reads and writes and the data matches for writes, although I don't know what you'd do if they didn't.Received on 2018-06-22 10:01:35
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