Re: 7501/8501 R/W gate in

On 8/30/20 8:26 PM, Francesco Messineo wrote:
> On Sun, Aug 30, 2020 at 7:54 PM Gerrit Heitsch
> <gerrit_at_laosinh.s.bawue.de> wrote:
>>
>>
>>> change state as in HI/LO or also change from driven to hi-z?
>>
>> High-Z is determined by AEC and if the CPU has been taken off the bus,
>> TED will drive R/W to HIGH.
> 
> ok perfect, that makes sense (and it's a lot easier to implement).
> 
>>
>>
>>>> Don't forget that a 264 system changes the CPU clock between normal and
>>>> double clock unless you set the right bit in TED. With the Gate IN, the
>>>> R/W=LOW part of a write cycle is the same length no matter what the CPU
>>>> clock.
>>>
>>> hm so a RAM cycle lasts the same time regardless of the CPU clock? I
>>> don't get this, how is that useful? You can't use the phi-low
>>> phase for refresh then? What am I missing again?
>>
>> You're missing that TED clocks the CPU only on double clock if it
>> doesn't need the bus itself for display data or DRAM refresh. So during
>> the 5 refresh cycles per scan line, the CPU is on single clock, no
>> matter if display is on or has been turned off, refresh always happens.
> 
> ok indeed I didn't know this, I'm starting to get a picture
> 
>>
>> Also how is this useful? That is simple. If the RAM cycle is always the
>> same length, you don't need to change any of the RAM control signals
>> which are generated by TED.
> 
> ok but then the RAM cycle length must always be the "short" one (or
> leak into phi2-low phase when the clock is fast) since a 6502 will
> always read or write to memory at every clock cycle, even if the byte
> read isn't needed (or it writes the wrong value, then write the good
> one at the next cycle).

It is always the short one. Since either the CPU runs on double clock 
and uses all available cycles the DRAM controller inside TED generates 
or it has to alternate RAM access with TED.



>>>>> 3) Why on a C64 there was no need for this R/W latch? What main difference
>>>>> exist between a C64 DRAM access and a C16 DRAM access (that I don't get)?
>>>>
>>>> Changing CPU clock speed probably.
>>>
>>> I still don't get it, if you change clock speed, the read/write cycle
>>> should lengthen or shorten accordingly.
>>
>> It doesn't on a 264 system, /RAS and /CAS timings don't change when the
>> CPU clock changes.
> 
> ok I see then that on fast clock, the 6502 core would raise R/W early
> if that wasn't gated. Of course, a 6510 with no R/W latch
> works fine it seems, so the RAMs don't seem to care much about this.

DRAMs don't seem to, but when I replaced the DRAM in one of my C16 with 
an SRAM, I had to gate R/W again and make sure R/W can only be LOW as 
long as PHI0 is HIGH. Without this circuit, the system wasn't stable. 
The DRAM being a 55ns part might have something to do with it.

  Gerrit