On Sun, Aug 30, 2020 at 8:41 PM Gerrit Heitsch <gerrit_at_laosinh.s.bawue.de> wrote: > > > > ok I see then that on fast clock, the 6502 core would raise R/W early > > if that wasn't gated. Of course, a 6510 with no R/W latch > > works fine it seems, so the RAMs don't seem to care much about this. > > DRAMs don't seem to, but when I replaced the DRAM in one of my C16 with > an SRAM, I had to gate R/W again and make sure R/W can only be LOW as > long as PHI0 is HIGH. Without this circuit, the system wasn't stable. > The DRAM being a 55ns part might have something to do with it. isn't what you did go "against" the latch action? I mean, if you make sure R/W stays low only on phi0 high (which a 6502's core should already do anyway), you are just defeating the R/W low lengthening that happens because of the gated latch. Or am I wrong again? When I have a working CPU again, I was also thinking of upgrading the RAM on my C16, but I might just use 2 x 64kx4 drams, that seems just easier than converting all for SRAM interfacing. Frank > > Gerrit > >Received on 2020-08-30 21:01:15
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