On 6/1/2021 11:52 AM, smf wrote: > I'm pretty sure they aren't seperate enough for the vic2 and cpu to have > access to different areas of ram at exactly the same time. I disagree. It's trivial to push the address and data lines for the VIC-II and a 64kB SRAM into a set of buffers that are tristated and only when the CPU needs to access that area. The only trick is handling the CPU clock for the edge case where the CPU wants to write to that bank of SRAM and the VIC-II is currently using stolen cycles. The quick and dirty option would be to simply stretch the CPU clock until the cycle stealing is over. Even the non static NMOS core should be stable for a line of cycles. But, to your other point, it's also easy to time slice access to the SRAM, thought it requires more logic (a CPLD would be good in that case). JimReceived on 2021-06-01 20:00:03
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