In the case of the p500 where the vic2 and cpu can access bank 15 or bank 0 or bank 1 then it would be impractical to have the cpu full speed access to any of the three (i.e. they could put in a 2mhz cpu) and only slowing down if the vic2 was accessing a different bank. I don't think you would ever want an exclusive sram for vic2 that the cpu has occassional access to. You want cpu+vic2 to have access to all memory inside the computer with as little overhead as possible. Potentially I would add extra banking bits to vic2 so it could access ram > 64k. On 01/06/2021 18:22, Jim Brain wrote: > I disagree. It's trivial to push the address and data lines for the > VIC-II and a 64kB SRAM into a set of buffers that are tristated and > only when the CPU needs to access that area. The only trick is > handling the CPU clock for the edge case where the CPU wants to write > to that bank of SRAM and the VIC-II is currently using stolen > cycles. The quick and dirty option would be to simply stretch the > CPU clock until the cycle stealing is over. Even the non static NMOS > core should be stable for a line of cycles. > >Received on 2021-06-01 20:00:22
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