On 6/1/2021 12:37 PM, smf wrote: > In the case of the p500 where the vic2 and cpu can access bank 15 or > bank 0 or bank 1 then it would be impractical to have the cpu full speed > access to any of the three (i.e. they could put in a 2mhz cpu) and only > slowing down if the vic2 was accessing a different bank. > > I don't think you would ever want an exclusive sram for vic2 that the > cpu has occassional access to. You want cpu+vic2 to have access to all > memory inside the computer with as little overhead as possible. > > Potentially I would add extra banking bits to vic2 so it could access > ram > 64k. Your comments are not in line with the original request for information. The original question was about using an '816 and a VIC-II with some unused C64 ICs to create an environment where the VIC-II and the CPU could run at full speed. The stated design parameters was a 64kB block of RAM for VIC-II: "The idea is to have 64K of memory exclusive to the VIC-II mapped into the memory address of the '816" You're changing the nature of the request. Creating a design where the VIC-II AND the 816 have access to all 16MB of address space as fast as possible presents a far more complicated design requirement.Received on 2021-06-01 20:00:53
Archive generated by hypermail 2.3.0.