Theorizing: chip select lines as clock speed selectors in a overclocked 6510 on a C64

I was reading about the CPU accelerators and the several overclocking projects for the Commodore 64.

It seems that the VIC-II and SID 'must' have their registers accessed at ~1Mhz.

The CIA chips are designed to run at ~1Mhz, and the 'A' versions at ~2Mhz.

The memory chips can run up to ~3 or ~4 megahertz, varied on the part used (120ns, 200ns).

The 74LS family of chips can AFAIK reliably run up to ~28Mhz but that's what I've found on the datasheets and my own (surely wrong) calculations.

Enter a 'synthesized' 6510 (I mean, a fpga'ed version, or a MCU based core, you name it) that I will call S6510

If I would want to have the S6510 working in a real C64 motherboard, what I would have to do is make it work in the higher frequency possible with the chips mentioned above. And yes, it would have to coexist with the VIC-II.

Who decides which chip will be activated when accessing this or that memory address? The PLA.

So the idea here is that the PLA would control also a clock divider that would decide the clock speed would the S6510 be running at, depending on the chip select output. 

The clock divider would have its base clock at DOT clock, using the internal C64 clock circuit. That would ensure that when divided by eight it would be properly in sync with the rest of the chips of the system. It's just what the VIC-II does. I'll call that input ICLK.

From there, every output of the clock divider would go to the chips that would support the clock speed that output would give.

The ICLK/8 output would be connected to the phi2 inputs of the SID and the CIAs. The VIC-II needs no phi2 input because it's already synced with /CS when /CS goes low.

And then there would be several other clock divider ouputs that would drive memory chips, that could be used depending on the rated speed of the chips used. So having

ICLK/4 would give 2Mhz
ICLK/4 would give 2Mhz
ICLK/4 would give 2Mhz