Re: Theorizing: chip select lines as clock speed selectors in a overclocked 6510 on a C64

On 6/30/2022 4:36 AM, Baltissen, GJPAA (Ruud) wrote:
>> But, if that's what you want, then triggering on the falling edge seems enough. (and yes, checking BA is needed as well).
> The C64/128 needs (almost) a complete top half of the clock to read or write data. So the faster device _has_ to detect the rising edge first so it can halt to meet this timing limitation. After the falling edge it can continue at full speed. Just pops up: this is IMHO exactly what the SuperCPU does when it has to access the C64/128.

I can't argue that point.  I misunderstood your initial post as trying 
to wait until the entire top half of the cycle was seen and then doing 
work, and if that is needed, then only the falling edge detection is needed.

Now that I understand your point (you need to detect the PHI2 cycle 
early enough in the cycle to ensure you have enough time to read/write 
memory in the 64), I take your comment as describing a circuit that 
triggers on the rising edge of PHI2 to place address and data and 
removes (tristates) address and data from the bus on the falling edge.  
That way, you ensure that data and address lines are valid long enough 
for the VIC address demux to do it's work and the RAM to accept the 
address and data for storage or the address alone for reading.

Jim