RE: Theorizing: chip select lines... (continued after mistake)

From: Baltissen, GJPAA (Ruud) <"Baltissen,>
Date: Thu, 23 Jun 2022 05:49:03 +0000
Message-ID: <PAXPR10MB55202E3B76C231EEF86CCB8BE1B59_at_PAXPR10MB5520.EURPRD10.PROD.OUTLOOK.COM>
> One CPU cycles takes 500ns. Wouldn't be actually that useful that one CPU would take 125ns, so a 'batch' of four CPU cycles could be run while the VIC-II waits for its turn to take on memory again?

This has already been done in February 1994: replacing the 6510 with a 3 MHz 6502 + some I/O. The whole was configured so that two top halves and one bottom half of the clock for the 6510 fitted in the top half of the original clock and two bottom halves and one tophalf of the clock for the 6510 fitted in the bottom half. Source: 64'er.

But coming back on your idea: IMHO much too much trouble and 'if's. The SuperCPU and other cartridges, like the Turbo Chameleon, already showed one way how it can be done: do everything in your own hardware and access the original board only when needed.
Personally I prefer to replace the 6510 with other hardware. One of the advantages: direct control of the 6510 I/O lines.


With kind regards / Met vriendelijke groet, Ruud Baltissen

http://www.baltissen.org





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Received on 2022-06-23 08:02:45

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