Re: Theorizing: chip select lines... (continued after mistake)

From: groepaz_at_gmx.net
Date: Thu, 23 Jun 2022 07:01:24 +0200
Message-ID: <276008885.ifERbkFSEj_at_rakete>
Am Donnerstag, 23. Juni 2022, 06:40:23 CEST schrieb Gerrit Heitsch:
> On 6/22/22 23:15, Jesus Cea wrote:
> > On 22/6/22 21:24, tokafondo_at_tokafondo.name wrote:
> >> YIKES!!! I pressed 'sent' by mistake and didn't had completed the post!!!
> > 
> > Remember than RAM is accessed twice per cycle: CPU and VIC-II.
> > 
> > If I would design a fast 6502-like accelerator I would interpose a fast
> > cache (write thru with a small (maybe 1-2-4 bytes) write buffer) or,
> > using something like a 65816, fast and exclusive RAM in other banks.
> > 
> > Dynamically adjusted 6502 frequency will not get you anything useful,
> > because 6502 do a memory cycle per CPU clock, always, even when not
> > useful at all. Too complicated, too little gain.
> 
> Didn't they do that in the C128 when running at 2 MHz?

it uses clock stretching when accessing i/o, yes


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Received on 2022-06-23 08:00:02

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