Theorizing: chip select lines... (continued after mistake)

From: tokafondo_at_tokafondo.name Date: Wed, 22 Jun 2022 19:24:58 +0000 Message-ID: <847782005ce273fcd13aba4069f0c3d1_at_tokafondo.name>

YIKES!!! I pressed 'sent' by mistake and didn't had completed the post!!! 

I will continue here

[...]

And then there would be several other clock divider ouputs that would drive memory chips, that
could be used depending on the rated speed of the chips used. So having

ICLK/4 would give 2Mhz
ICLK/2 would give 4Mhz

...and so.

The memory chips could be replaced by parts that would allow for higher speeds while having enough
retention time in lower speeds.

Do you think the chip select outputs of the PLA could be used in such a way???