> You should also satisfy the RDY line's prerequisites, look at the 6502 datasheet for that. For this > statement : "If ready is low during a write cycle, it is ignored until the following read > operation" Yes. The eCPU (external CPU) has its own terms and conditions to have it paused. > > Most implementations have a counter of some sorts to count phi2 up to 3 (can't confirm it as > visual6502 org is down) > > You can take a look at freezer cartridge schematics (they don't use it for dma but they satisfy the > same condition for safe entry) or vhdl code of 1541 ultimate or similar. > > Also BA condition is strongly tied to the operation of VIC2, with the counting operation to satisfy > RDY, BA could change state. In the famous "vic-ii.txt" document where detailed working of the VIC2 is shown, it's said that this chip does a read access in every cycle, even when it's not needed. I will investigate more on that, because that could mean that BA is asserted no matter what. > > For testing though, you could disable the screen so VIC2 is out of equation... > On Sun, Jul 10, 2022 at 12:29 PM <tokafondo_at_tokafondo.name> wrote: > >> Thanks both for your useful and detailed answers. >> >> It seems to me that a sort of combination between NAND'ing the different lines that qualify the DMA >> could do the trick, with some mechanism that would make the external CPU wait that for it to >> happen. >> >> Something like >> >> - The external CPU (eCPU) asks for DMA. >> - An external circuit acknowledges that petition and pulls eCPU's RDY line low in its own terms to >> make it wait for the DMA authorization. >> - PHI2 goes high: that should mean the internal CPU (iCPU) in in charge. >> - BA line goes high: that should mean the VIC-II has released the bus. >> - R-/W goes high: that would mean iCPU (when appropiate) finished writing. >> >> When those last three conditions met, I think it can be concluded that it's safe to assume that >> iCPU is ready to be stopped, isn't it? >> >> - So those three 'highs' could be NAND'ed and they could pull /DMA low with a latch so iCPU is >> stopped, and that would pull eCPU RDY high as a signal of 'go ahead but in sync with VIC-II', >> because the BA line and DOT/PHI2 lines would be also linked to eCPU RDY input. >> >> Timing is also crucial, of course... >> >> What do you think?Received on 2022-07-10 18:00:07
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