Definition of BA : "With this signal, the VIC indicated that the bus is available to the processor during the second clock phase (ø2 high)", I assumed* you are only interested in the cpu part of the whole clock signal (ø2 high) . Disabling the display eliminates badlines / sprite fetches and other extra memory accesses which VIC steals from the cpu's phase. *If VIC can't be put off the bus on the first phase of the clock then it's more like the only choice rather than assumption. There might also be the possibility of fighting the VIC on the bus but I've not seen anything documented about that anywhere. Of course there is an additional possibility of just controlling the data bus on ø2 low... which would need an address decoding change and would be a very specific endeavour. On Sun, Jul 10, 2022 at 6:08 PM <tokafondo_at_tokafondo.name> wrote: > > > In the famous "vic-ii.txt" document where detailed working of the VIC2 is > shown, it's said that this chip does a read access in every cycle, even > when it's not needed. I will investigate more on that, because that could > mean that BA is asserted no matter what. > > >Received on 2022-07-10 18:02:33
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