Re: Modern, but fully compatible 6502? [and testing suite]

From: groepaz_at_gmx.net
Date: Sun, 04 Sep 2022 21:43:24 +0200
Message-ID: <9782463.tdPhlSkOF2_at_rakete>
Am Sonntag, 4. September 2022, 21:30:31 CEST schrieb silverdr_at_srebrnysen.com:
> > On 2022-09-04, at 18:43, Ed Spittles <ed.spittles_at_gmail.com> wrote:
> >
> > I've just remembered - one of the early successes from the visual6502
> > project was Peter Monta's implementation of the core algorithm on an
> > FPGA, running fast enough to work as a 1MHz 6502 in an Atari, using a
> > GODIL module.
>
> Interesting! GODIL modules (AFAIR) were (are?) CPLD based?
>
> http://www.oho-elektronik.de/index.php?c=1&s=product1
>
> These ones? There's one Spartan FPGA based but all are with small pincount.
> The larger ones apparently are no longer there.
>
> Do you have more info/reference on that particular implementation?
>
> Oh, and I trust there must be a comprehensive compatibility testing "suite"
> for that somewhere? I vaguely recall something running on a 1541... was it
> from VICE team?

That was probably the lorenz suite (which ninja ported to the 1541), its all
in the vice testbench, see

https://sourceforge.net/p/vice-emu/code/HEAD/tree/testprogs/general/
Lorenz-2.15/

and

https://sourceforge.net/p/vice-emu/code/HEAD/tree/testprogs/CPU/

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<Michael Swaine>
Received on 2022-09-04 22:03:23

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