> tokafondo_at_tokafondo.name wrote on 03.09.2022 22:24: > >> But there is no other limitation for the existence of more registers, bigger memory addressing >> capacity [...] > > Actually, there is. Adding more registers, addressing modes etc means that the list of opcodes gets > longer than 256, so you need to use more than one byte for each opcode. That means much longer > programs and much more complicated opcode decoding. Well... for a pen and paper design like the original 6502 was, that would surely be a problem or at least more a daunting task. But what about the tools that are used today for designing electronics? Add another byte to the opcode table and now there is room for 4096 opcodes. Maybe that would just be too much. I've found that "The x86 architecture has 8 General-Purpose Registers (GPR), 6 Segment Registers, 1 Flags Register and an Instruction Pointer. 64-bit x86 has additional registers." and "According to Intel's XED, as of this writing [2016], there are 1503 defined x86 instructions (“iclasses” in XED lingo), from AAA to XTEST (this includes AMD-specific extensions too, by the way)". So it seems that yes, things could be more difficult and complicated, but not impossible. > Regards,Michau.Received on 2022-09-04 23:00:03
Archive generated by hypermail 2.3.0.