Re: C128 and 8MHz Z80 (revisited)

On 6/5/2024 5:17 PM, Maciej Witkowiak wrote:
>
> Thanks!
>
> I have a dev board with xc9572xl, but haven't got around to install 
> any programming enviroment yet.
> Now that I see that this has a chance to work I will surely give it a try.

If you are using Linux, it should be easy (Xilinx WebPack ISE dload).  
If using Windows 10/11, shoot me a personal email, as it's not tough, 
but it requires replacing a DLL to get it to work.

>
> I'm no expert on Z80 either so ez80 at this time is out my skill set, 
> but surely I can start with replicating this circuit - that I already 
> understand.

I had a moment between jobs, so I converted the CUPL to Verilog (or at 
least, I tried.  I had to double negate a few things, so I hope I got 
that done correctly), and I put the flop into the CPLD.

I laid out a quick board to check on placement.  It's not clean, and I 
really need to switch my workflow to KiCAD (it's on the box here, and I 
can use it), but I can fly in EAGLE v7, so I just went ahead and laid it 
out.  Since you've proved the idea, I left off a few of your test 
jumpers, but left CLK_SEL.

WIth the 72 pin CPLD (of which I have a ton, no supply worries there), 
it uses 10 or so pins, 1 flip flop, and 4 macro cells.  I thought about 
pushing more signals into the CPLD, but I thought I'd wait to see what 
is interesting, as I barely know the Z80 bus.  But, you could easily 
pull in all the non Address/Data signals, and with a bit of layout, you 
can pull all the address and data lines in (put the speed under SW 
control, if desired).  I also need to add in a third clock source, which 
is a PLL that runs off the dot cock but multiplies the dot clock (with 
low skew):

Datasheet: https://www.renesas.com/us/en/document/dst/501-datasheet

By default, it doubles the input clock, but can do 2x,3x,4x,5x,6x,and 
8x, and also some factions.


>
>     And my CUPL is bad as well, but I can give it a try to load the Flop
>     into the GAL.
>
>
> I would welcome any ideas. Also if it would be easier for you to 
> express it in Verliog that would help me learn too.
Yeah, since my CUPL is really bad, time is short, and you're not opposed 
to the idea, it was easier to just do it in Verilog.
>
> Here is how it is supposed to work:
>
> 0 VIC cycle phase starts, latch is in reset state, latch D input is 
> constant 1, but due to reset Q output is 0 and negated /Q is 1; Z80 is 
> stopped as its clock is held low
> 1) Z80 cycle phase starts, latch goes out of reset, /Q output = 
> WAITLATCH stays 1, Z80 sees that as inactive /WAIT and runs program, 
> without bus access requests WAITTRIGGER stays 0
> 2) Z80 wants to access the bus, WAITTRIGGER will rise to 1; this will 
> cause latch D input connected to 1 be copied to the output, so /Q 
> becomes 0, Z80 will see that as an active /WAIT and will stop
> 3) this state will not change until start of the next VIC cycle phase
> 4) VIC cycle phase starts, latch is reset - will set latch /Q to 1, so 
> for Z80 /WAIT now becomes inactive; but Z80 won't run because during 
> this half-cycle the CPU clock signal is not passed at all
> 5) Z80 cycle phase starts, it can continue because after latch reset 
> /WAIT is inactive; Z80 accesses the bus so WAITTRIGGER stays 1 until 
> Z80 gets what it needs from data lines - then it goes back to 0
>
> The idea of this is that during Z80 clock phase when WAITTRIGGER goes 
> from inactive to active we can latch /WAIT line low to hold it low at 
> least until the start of VIC cycle.
> We release it before/at the start of Z80 cycle it so /WAIT becomes 
> high again - even though the latch trigger condition is still active.
>
> I guess that is something like asynchronous preset of /WAIT (based on 
> WAITTRIGGER) with synchronous reset (based on CLK1MHZ) but the preset 
> has to be edge triggered.
>
> Now that I wrote all of that I think that maybe I fixated too much on 
> /WAIT signal, I can't avoid flip-flop yet but it seems it could work 
> just as well by controlling the Z80 clock alone.

I was thinking the same, so I'd recommend adding in a lot of the signals 
you'd like to play with, and then you can wire them up in the CPLD and 
see what works best.

Adding in on board RAM is also possible, and using a few register bits 
to denote what parts of Z80 RAM you wish to mirror, if any.

I forked your github project and added my stuff into it my version:

https://github.com/go4retro/C128-Z80Plus

>
> ytm


-- 
Jim Brain
brain_at_jbrain.com  
www.jbrain.com