Re: C128 and 8MHz Z80 (revisited)

On 6/5/2024 5:17 PM, Maciej Witkowiak wrote:
>
By the way, I think the issue with the on board VDC 16MHz signal is that 
is is not aligned to the DOT CLOCK.  The DOT CLOCK is 8.18MHz (7.88MHz 
in PAL), but the VDC is exactly 16MHz, and it does not align with the 
DOT clock at all.  There's stories from Bil Herd about the lack of sync 
causing VDC register store issues in SW.

 From his Reddit AMA:

"The highest visibility one was we got the 8563 80 column chip back on 
the Friday before Christmas (CES show was the first week in January) and 
the fix for the fact it didn’t work at all in real usage actually made 
the problem worse. The engineer was in total denial of the need to 
synchronize the data and control lines due to the fact he had his own 
clock and lived in an asynchronous world. Everybody gathered around to 
watch it fail and it meant that a third of the CES booth would not be 
showable as well as CPM, so more than a third. While I was receiving 
condolences from the chip guys and the chip testing guys and the normal 
crew we ended up in a quick brainstorming session and I decided that I 
had nothing to lose by trying to create a PCB under the 80 column chip 
with a phase locked loop (PLL) on it."

And:

"Actually we knew about it and it turns out if you write to the register 
twice in a row with the same data it worked better (we called this a 
Texan Write as the engineer was from Texas, turns out the guy who 
designed the gate array on the 364 talking TED also did the same thing, 
we think it had something to do with the drinking water)."


-- 
Jim Brain
brain_at_jbrain.com
www.jbrain.com