RE: C128 and 8MHz Z80 (revisited)

My thought: what about using an asynchronous interface? I made one towards the expansion bus for the C64 once. Pre-condition: the 6510 is halted already, and that is the case here, and check BA.

For a read:
- wait until the Phi2 is (L)
- during Phi2 is (H), latch the data into 573 or equivalent
- after Phi2 goes (L), run on full speed again

During a write:
- wait until the Phi2 is (L)
- when Phi2 goes (H), output the data on the data bus and start waiting
- after Phi2 goes (L), run on full speed again

Main advantage: the above solution does not depend on the dot clock or whatever. One can use even a 10+ MHz (e)Z80.

A GAL can handle it. A flipflop is needed but even that the GAL can handle. Not by using the CLK input but by creating two NAND gates and in turn creating a flipflop using them.

Another option, but not tested: use a latch to write the data. If the device is not too fast, a possible next write will happen after Phi2 went (L).

Think about this and have fun!


With kind regards / Met vriendelijke groet, Ruud Baltissen

http://www.baltissen.org





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